S5T8555 - TIME SLOT ASSIGNMENT CIRCUIT

Description

A Transmit frame sync output which is normally low, and goes active-high for 8 cycles of BCLK when a valid transmit time slot assignment is made.

A Receive frame sync output which is normally low, and goes active-high for 8 cycles of BCLK when a valid receive time slot assignment is made.

Features

Single, 5V operation Low power consumption: 5mW Controls four 1 CHIP CODEC Independent transmit and receive frame syncs channel unidirectional mode Up to 64 time slots per frame Compatible with S5T8554B/7B CODECs TTL and CMOS compatible.

Samsung semiconductor

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Datasheet Details

Part number	S5T8555
Manufacturer	Samsung semiconductor
File Size	85.29 KB
Description	TIME SLOT ASSIGNMENT CIRCUIT
Datasheet	S5T8555 Datasheet
Additional preview pages of the S5T8555 datasheet.

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Full PDF Text Transcription

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TIME SLOT ASSIGNMENT CIRCUIT S5T8555 INTRODUCTION The S5T8555 is a per channel Time Slot Assignment Circuit (TSAC) that produces 8-bit receive and transmit time slots for four 1 CHIP CODEC.

Published: Apr 7, 2005 |