K4D261638K-LC50 - 128Mbit GDDR SDRAM

This page provides the datasheet information for the K4D261638K-LC50, a member of the K4D261638K 128Mbit GDDR SDRAM family.

Description

The K4D261638K is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG’s high performance CMOS technology.

Features

2.5V + 5% power supply for device operation.
2.5V + 5% power supply for I/O interface.
SSTL_2 compatible inputs/outputs.
4 banks operation.
MRS cycle with address key programs -. Read latency 2,3(clock) -. Burst length (2, 4 and 8) -. Burst type (sequential & interleave).
All inputs except data & DM are sampled at the positive going edge of the system clock.
Differential clock input.
Wrtie-Interrupted by Read Function.

Samsung

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Datasheet Details

Part number	K4D261638K-LC50
Manufacturer	Samsung
File Size	383.16 KB
Description	128Mbit GDDR SDRAM
Datasheet	K4D261638K-LC50 Datasheet
Additional preview pages of the K4D261638K-LC50 datasheet.

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Full PDF Text Transcription

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K4D261638K 128M GDDR SDRAM 128Mbit GDDR SDRAM 2M x 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM Revision 1.3 July 2007 Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2.

Published: Sep 1, 2016 |