Download K4H511638C-UC Datasheet PDF
K4H511638C-UC page 2
Page 2
K4H511638C-UC page 3
Page 3

K4H511638C-UC Key Features

  • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
  • Double-data-rate architecture; two data transfers per clock cycle
  • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
  • Four banks operation
  • Differential clock inputs(CK and CK)
  • DLL aligns DQ and DQS transition with CK transition
  • MRS cycle with address key programs
  • All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
  • Data I/O transactions on both edges of data strobe
  • Edge aligned data output, center aligned data input

K4H511638C-UC Description

32Mb x 16 64Mb x 8 128Mb x 4 DDR SDRAM VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM WE CAS RAS CS NC BA0 BA1 AP/A10 A0 A1 A2 A3 VDD VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NC NC WE CAS RAS CS.