Datasheet4U Logo Datasheet4U.com

K4S643232H-TC-L70 - 64Mb H-die (x32) SDRAM

General Description

The K4S643232H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Synchronous design allows precise cycle control with the use of system clock.

Key Features

  • JEDEC standard 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave).
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst read single-bit write operation.
  • DQM for masking.
  • Auto & self refresh.
  • 64ms refresh period(4K Cycle).

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
K4S643232C 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL Samsung semiconductor
K4S643232E 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL(3.3V) Samsung semiconductor
K4S643232F 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL Samsung semiconductor
K4S643233F-SDE 2Mx32 Mobile SDRAM 90FBGA CMOS SDRAM Samsung semiconductor
K4S643233F-SDI 2Mx32 Mobile SDRAM 90FBGA CMOS SDRAM Samsung semiconductor

Other Datasheets by Samsung Semiconductor

Part Number Description
K4S643232H-TC-L50 64Mb H-die (x32) SDRAM
K4S643232H-TC-L55 64Mb H-die (x32) SDRAM
K4S643232H-TC-L60 64Mb H-die (x32) SDRAM
K4S643232H-UC-L50 2M x 32 SDRAM
K4S643232H-UC-L55 2M x 32 SDRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
SDRAM 64Mb H-die (x32) CMOS SDRAM 64Mb H-die (x32) SDRAM Specification Revision 1.3 February 2004 *Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev. 1.3 February. 2004 SDRAM 64Mb H-die (x32) Revision History Revision 0.0 (June, 2003) - Target spec First release. Revision 0.1 (July, 2003) - Delete speed 4.5ns. Revision 0.2 (September, 2003) - Preliminary spec release. Revision 1.0 (November, 2003) - Final spec release Revision 1.1 (December, 2003) - Corrected typo Revision 1.2 (December, 2003) - Modified load cap 50pF -> 30pF & Typo Revision 1.3 (February, 2004) - Corrected typo. CMOS SDRAM - 2 - Rev. 1.3 February. 2004 SDRAM 64Mb H-die (x32) 512K x 32Bit x 4 Banks SDRAM FEATURES • JEDEC standard 3.