K7A403600M Datasheet PDF - Samsung 128K x 36 Synchronous SRAM Specs

K7A403600M - 128K x 36 Synchronous SRAM

Datasheet Summary

Description

The K7A403600M is a 4,718,592-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System.

Features

Synchronous Operation.
2 Stage Pipelined operation with 4 Burst.
On-Chip Address Counter.
Self-Timed Write Cycle.
On-Chip Address and Control Registers.
VDD= 3.3V+0.3V/-0.165V Power Supply.
VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O.
5V Tolerant Inputs Except I/O Pins.
Byte Writable Function.
Global Write Enable Controls a full bus-width write.
P.

Datasheet Details

Part number	K7A403600M
Manufacturer	Samsung
File Size	307.80 KB
Description	128K x 36 Synchronous SRAM
Datasheet	K7A403600M Datasheet
Additional preview pages of the K7A403600M datasheet.

📁 Similar Datasheet

K7A403600B - 128K x 36 / x 32 & 256K x 18 Synchronous SRAM (Samsung semiconductor)

K7A403601B - 128Kx36 & 128Kx32 Synchronous SRAM (Samsung semiconductor)

K7A403609A - 128Kx36 & 256Kx18-Bit Synchronous Pipelined Burst SRAM (Samsung semiconductor)

K7A403609B - 128Kx36/x32 & 256Kx18 Synchronous SRAM (Samsung semiconductor)

K7A403200B - 128K x 36 / x 32 & 256K x 18 Synchronous SRAM (Samsung semiconductor)

K7A403201B - 128Kx36 & 128Kx32 Synchronous SRAM (Samsung semiconductor)

K7A403209B - 128Kx36/x32 & 256Kx18 Synchronous SRAM (Samsung semiconductor)

K7A401800B - 128K x 36 / x 32 & 256K x 18 Synchronous SRAM (Samsung semiconductor)

K7A401809A - 128Kx36 & 256Kx18-Bit Synchronous Pipelined Burst SRAM (Samsung semiconductor)

K7A401809B - 128Kx36/x32 & 256Kx18 Synchronous SRAM (Samsung semiconductor)

Full PDF Text Transcription

Click to expand full text

K7A403600M Document Title 128Kx36-Bit Synchronous Pipelined Burst SRAM 128Kx36 Synchronous SRAM Revision History Rev. No. 0.0 0.1 0.2 0.3 History Initial draft Change 7.5 bin to 7.2 Change speed symbol 6.0/6.7/7.2/8.5 to 60/67/72/85 Draft Date May . 15. 1997 January . 13 . 1998 February. 02. 1998 Remark Preliminary Preliminary Preliminary Preliminary Change DC characteristics VDD condition from VDD=3.3V+10%/-5% Change February. 12. 1998 Input/output leackage currant for ±1µA to ±2µA Modify Read timing & Power down cycle timing. Change ISB2 value from 30mA to 20mA. Remove DC characteristics ISB1 - L ver.& ISB2 - L ver . Remove Low power version. Add 119BGA(7x17 Ball Grid Array Package) Change Undershoot spec from -3.0V(pulse width≤20ns) to -2.0V(pulse width≤tCYC/2) Add Overshoot spec 4.

Published: Aug 2, 2013 |