Datasheet4U Logo Datasheet4U.com

KM684002A - 512Kx8 Bit High Speed Static RAM

General Description

The KM684002A is a 4,194,304-bit high-speed Static Random Access Memory organized as 524,288 words by 8 bits.

The KM684002A uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle.

Key Features

  • Fast Access Time 15,17,20ns(Max. ).
  • Low Power Dissipation Standby (TTL) : 50mA(Max. ) (CMOS) : 10mA(Max. ) Operating KM684002A - 15 : 170mA(Max. ) KM684002A - 17 : 165mA(Max. ) KM684002A - 20 : 160mA(Max. ).
  • Single 5.0V±10% Power Supply.
  • TTL Compatible Inputs and Outputs.
  • I/O Compatible with 3.3V Device.
  • Fully Static Operation - No Clock or Refresh required.
  • Three State Outputs.
  • Center Power/Ground Pin Configuration.
  • Sta.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
KM681000C 128K x8 bit Low Power CMOS Static RAM Samsung semiconductor
KM681000E 128Kx8 bit Low Power CMOS Static RAM Samsung semiconductor
KM681001A 128K x 8 Bit High-Speed CMOS Static RAM Samsung semiconductor
KM681001A 128K x 8 Bit High-Speed CMOS Static RAM Samsung semiconductor
KM681001B 128K x 8 Bit High-Speed CMOS Static RAM Samsung semiconductor

Other Datasheets by Samsung Semiconductor

Part Number Description
KM684002AE 512Kx8 Bit High Speed Static RAM
KM684002AI 512Kx8 Bit High Speed Static RAM
KM684002 512Kx8 Bit High Speed Static RAM(5V Operating) / Revolutionary Pin out
KM684002E 512Kx8 Bit High Speed Static RAM
KM684002I 512Kx8 Bit High Speed Static RAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
PRELIMINARY KM684002A, KM684002AE, KM684002AI Document Title 512Kx8 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out. Operated at Commercial Temperature Range. CMOS SRAM Revision History Rev No. Rev. 0.0 Rev. 0.5 History Initial release with Design Target. Release to Preliminary Data Sheet. 0.1. Replace Design Target to Preliminary. 0.2. Delete 12ns part but add 17ns part. 0.3. Relax D.C and A.C parameters and insert new parameter(Icc1) with the test condition. 0.3.1. Insert Icc1 parameter with the test condition as address is increased with binary count. 0.3.2. Relax D.C and A.C parameters. Previous spec. Relaxed spec.