DESCRIPTION
Interrupt mode register Reset Value 0x00000000 31 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTMOD X X X X X X X X X X X X X X X X X X X X X [20:0] Interrupt mode bits NOTE: Each of the 21 bits in the interrupt mode enable register, INTMOD, corresponds to an interrupt source. When the source interrupt mode bit is set to 1, the interrupt is processed by the ARM7TDMI core in FIQ (fast interrupt) mode. Otherwise, it is processed in IRQ mode (normal interrupt). The 21 interrupt sources are mapped as follows: [20] I 2C interrupt [19] Ethernet controller MAC Rx interrupt [18] Ethernet controller MAC Tx interrupt [17] Ethernet controller BDMA Rx i nterrupt [16] Ethernet controller BDMA Tx interrupt [15] HDLC channel B Rx interrupt [14] HDLC channel B Tx interrupt [13] HDLC channel A Rx interrupt [12] HDLC channel A Tx interrupt [11] Timer 1 interrupt [10] Timer 0 interrupt [9] GDMA channel 1 interrupt [8] GDMA channel 0 interrupt [7] UART1 receive & error interrupt [...
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