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KS32C50100 - Interrupt Controller

Download the KS32C50100 datasheet PDF. This datasheet also covers the KS32C50100-2 variant, as both devices belong to the same interrupt controller family and are provided as variant models within a single manufacturer datasheet.

Description

Interrupt mode register Reset Value 0x00000000 31 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTMOD X X X X X X X X X X X X X X X X X X X X X [20:0] Interrupt mode bits NOTE: Each of the 21 bits in the interrupt mode enable register, INTMOD, corresponds to an in

Features

  • ghest priority among the pendi.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (KS32C50100-2_Samsung.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Samsung Semiconductor

Part Number Description
KS32C50100 RISC Microcontroller
KS32C50100 32-Bit RISC Microcontroller
KS32C50100 32-Bit Timers
KS32C5000 32-Bit RISC Microcontroller
KS3A COLOR TELEVISION RECEIVER MANUAL

Full PDF Text Transcription

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KS32C50100 RISC MICROCONTROLLER INTERRUPT CONTROLLER 13 • • • INTERRUPT CONTROLLER The KS32C50100 interrupt controller has a total of 21 interrupt sources. Interrupt requests can be generated by internal function blocks and at external pins. The ARM7TDMI core recongnizes two kinds of interrupts: a normal interrupt request (IRQ), and a fast interrupt request (FIQ). Therefore all KS32C50100 interrupts can be categorized as either IRQ or FIQ. The KS32C50100 interrupt controller has an interrupt pending bit for each interrupt source. Four special registers are used to control interrupt generation and handling: Interrupt priority registers. The index number of each interrupt source is written to the pre-defined interrupt priority register field to obtain that priority.
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