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M312L2828ET0 - DDR SDRAM Registered Module

General Description

Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 DQS0 ~ DQS17 CK0,CK0 ~ CK2, CK2 CKE0, CKE1(for double banks) CS0, CS1(for double banks) RAS CAS WE CB0 ~ CB7 Function Address input (Multiplexed) Bank Select Address Data input/output Data Strobe input/output Clock input Clock enable input Chip select input Row

Key Features

  • DQS I/O 3 I/O 2 I/O 1 I/O 0 CS D11 DM DQS3 DQ24 DQ25 DQ26 DQ27 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS D3 DM DQS12 (DM3) DQ28 DQ29 DQ30 DQ31 DQS I/O 3 I/O 2.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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256MB, 512MB, 1GB Registered DIMM DDR SDRAM DDR SDRAM Registered Module 184pin Registered Module based on 256Mb E-die (x4, x8) with 1,700 / 1,200mil Height & 72-bit ECC Revision 1.4 January, 2004 Revision 1.4 February, 2004 256MB, 512MB, 1GB Registered DIMM Revision History Revision 1.0 (April, 2003) - First release Revision 1.1 (July, 2003) - Delete speed B3 Revision 1.2 (August, 2003) - Corrected typo. Revision 1.3 (January, 2004) - Corrected typo in functional block diagram of 1GB DIMM Revision 1.4 (February, 2004) - Corrected functional block diagram of 1GB DIMM DDR SDRAM Revision 1.