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M312L2920BG0 - DDR SDRAM Registered Module

General Description

Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 DQS0 ~ DQS17 CK0,CK0 ~ CK2, CK2 CKE0, CKE1(for double banks) CS0, CS1(for double banks) RAS CAS WE CB0 ~ CB7 Function Address input (Multiplexed) Bank Select Address Data input/output Data Strobe input/output Clock input Clock enable input Chip select input Row

Key Features

  • 3 I/O 2 I/O 1 I/O 0 CS DM D4 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS13 (DM4) DQ36 DQ37 DQ38 DQ39 D22 DQS I/O 0 I/O 1 I/O 2.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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1GB, 2GB Registered DIMM DDR SDRAM DDR SDRAM Registered Module (60FBGA) 184pin Registered Module based on 512Mb B-die (x4, x8) with 1,200mil Height & 72-bit ECC Revision 1.1 August. 2003 Rev. 1.1 August. 2003 1GB, 2GB Registered DIMM Revision History Revision 1.0 (July, 2003) - First release Revision 1.1 (August, 2003) - Corrected typo. DDR SDRAM Rev. 1.1 August.