M312L2923BG0-CB3 Datasheet | Samsung Semiconductor

Feature - Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V - Double-data-rate architecture; two data transfers per clock cycle - Bidirectional data strobe(DQS) - Differential clock inputs(CK and CK) - DLL aligns DQ and DQS transition with CK transition - Programmable Read latency 2, 2.5 (clock) - Programmable Burst length (2, 4, 8) - Programmable Burst type (sequential & interleave) - Edge aligned data output, center aligned data input - Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) - Serial presence detect with EEPROM SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. Rev. 1.1 August. 2003 1GB, 2GB Registered DIMM Pin Configuration (Front side/back side) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Front VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC /RESET VSS DQ8 DQ9 DQS1 VDDQ - CK1 - /CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 Pin 32 33 34 35 36 37 38 39...