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M312L6523BTS-CAA - DDR SDRAM Registered Module

General Description

Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 DQS0 ~ DQS17 CK0, CK0 CKE0, CKE1(for 2 Row) CS0, CS1(for 2 Row) RAS CAS WE CB0 ~ CB7 Function Address input (Multiplexed) Bank Select Address Data input/output Data Strobe input/output Clock input Clock enable input Chip select input Row address strobe Column a

Key Features

  • I/O 2 I/O 1 I/O 0 C S D M D11 DQS3 DQ24 DQ25 DQ26 DQ27 D Q S I/O 3 I/O 2 I/O 1 I/O 0 C S D M DQS12 (DM3) D Q 2 8 D Q 2 9 D Q 3 0 D Q 3 1 D3 D Q S I.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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512MB, 1GB, 2GB TSOP Registered DIMM DDR SDRAM DDR SDRAM Registered Module ( TSOP-II ) 184pin Registered Module based on 512Mb B-die with 1,700 / 1,200mil Height & 72-bit ECC Revision 1.0 December. 2003 Revison 1.0 December, 2003 512MB, 1GB, 2GB TSOP Registered DIMM Revision History Revision 0.0 (February, 2003) - First release Revision 0.1 (July, 2003) - Deleted speed B3 Revision 0.2 (August, 2003) - Corrected typo. Revision 1.0 (December, 2003) - IDD current revision. - Finalized DDR SDRAM Revison 1.