SR71010A Datasheet | Sandcraft

features that minimize power consumption. The high performance system interface, which is fully patible to R4xxx/5xxx/7xxx Sys AD interface, can operate up to 133MHz with split transactions and out- of- order return. The SR71010A includes a high - per formance floating point unit (FPU) that is fully MIPS64 pliant. The FPU is decoupled from the integer pipeline enabling autonomous integer and floating point operations. i TLB PC gen i-cache decode BHT buffer Sys AD & L3 Interface register file dispatch FP reg file dispatch ALUx ALUy LD/ST d TTB MOV TB LOAD MATH MACC Dcache L2 cache L3 tags SR71010A Architecture Block Diagram High performance architecture - Fully MIPS64 Instruction Set Architecture (ISA) pliant True 2-way superscalar architecture - Dual fetch, dual dispatch, up to 6-issue, up to 6-execute, dual-mit - Maximum operation rate of pipeline: 2 instructions per cycle - Out-of-order issue and dispatch - In-order retires 9-stage pipeline for high clock frequency - Optimized pipeline bypass architecture for minimizing instruction interdependent stalls Intelligent dynamic branch prediction - Bi-modal 3Kbit table, Branch predictor - Keeps pipeline full and minimizes branch mis-predict penalties - Speculative execution down predicted paths - Maximizes sustainable performance Low power consumption - Fully static design - Clock enabled registers for improved power management - Dynamic activation of sense amps. in caches High-performance system interface - patible with R4xxx/5xxx/7xxx Sys AD interface - 133 MHz with split transactions and out-of-order return High-performance floating point TM - Fully MIPS64 pliant - IEEE - 754 patible - Decoupled from Integer pipeline Extended...