SR71040A Datasheet | Sandcraft

features : - - - - - - 600 to 800MHz two-way superscalar 9 stage pipeline with out of order executions and hardware branch prediction. Primary instruction and data caches are both 16KB, and 2-way set associative On-chip secondary cache is 128KB and is 4-way set associative 133MHz Sys AD bus interface IEEE 754 patible floating point unit The SR71040A is available in two speed grades of 600MHz and 800MHz in a 256 pin TBGA package. i TLB PC gen i-cache decode register file dispatch BHT buffer FP reg file dispatch Sys AD ALUx ALUy LD/ST d TLB MOV TB LOAD MATH MACC Dcache L2 cache SR71040A Architecture Block Diagram High performance architecture - Fully MIPS64 Instruction Set Architecture (ISA) pliant True 2-way superscalar architecture - Dual fetch, dual dispatch, up to 6-issue, up to 6-execute, dual-mit - Maximum operation rate of pipeline: 2 instructions per cycle - Out-of-order issue and dispatch - In-order retires 9-stage pipeline for high clock frequency - Optimized pipeline bypass architecture for minimizing instruction interdependent stalls Intelligent dynamic branch prediction - Bi-modal 3Kbit table, Branch predictor - Keeps pipeline full and minimizes branch mis-predict penalties - Speculative execution down predicted paths - Maximizes sustainable performance Low power consumption - Fully static design - Clock enabled registers for improved power management - Dynamic activation of sense amps. in caches High-performance system interface - patible with R4xxx/5xxx/7xxx Sys AD interface - 133 MHz with split transactions and out-of-order return High-performance floating point - Fully MIPS64 pliant - IEEE - 754...