PG001M Overview
V DD=5V, CL=15pF See Fig. H level time, VDD=5V L level time, VDD=5V Inter-clock See Fig. 3.5 −0.3 µA V V pF MHz ns ns AC characteristics Output voltage Rise and fall time CLOCK IN terminal Input clock time Reset setting time (A) Stabilization time after reset (B) Signal setting time (C) Stabilization time after signal input (D) µs ns S 100 ns Fig.
