Description
4-bit Input/output port
Data direction can be specified for each bit
Use of pull-up resistor can be specified for each bit
Other functions P70: INT0 input/HOLD release input/Timer0L capture input /Output for watchdog timer P71: INT1 input/HOLD r
Features
- (1) Read Only Memory (ROM) - 65535 × 8 bits (LC875064B) - 57343 × 8 bits (LC875056B) - 49151 × 8 bits (LC875048B)
Ver.1.03 12500
91400 RM (IM) HK / SY No.6714-1/26
LC875064B/56B/48B (2) Random Access Memory (RAM) - 2048 × 8 bits (LC875064B/56B/48B) (3) Bus Cycle Time - 100ns (10MHz) Note: The bus cycle time indicates ROM read time. (4) Minimum Instruction Cycle Time : 300ns (10MHz)
(5) Ports - Input/output ports Each bit data direction programmable Nibble data direction programmable - Input.
LC875048B Datasheet
