LC89975M Overview
EN 5391 NMOS + CCD LC89975M PAL-Format Delay Line Preliminary Overview The LC89975M is a lower-cost PAL-Format CCD delay line based on the LC89970M, with the sizes of chip and package miniaturized and the external parts count reduced. Auto-bias circuit Sync tip clamping circuit (luminance signal) Center bias circuit (chrominance signal) Sample-and-hold circuit PLL 3× circuit 3·fsc clock output circuit RD voltage...
LC89975M Key Features
- 5 V single-voltage power supply
- On-chip 3× PLL circuit for 3-fsc operation from an fsc (4.43 MHz) input
- Supports PAL/GBI and 4.43 NTSC systems, selected by a control pin input
- Includes an on-chip b filter for chrominance signal crosstalk exclusion. This adjustment-free circuit provides high-prec
- Peripheral circuits included on chip to allow operation with minimal external circuits
- Positive-phase signal input, positive phase signal output (luminance signal)
- CCD shift register (for chrominance and luminance signals)
- CCD drive circuit
- Circuit for switching the number of CCD stages
- CCD signal addition circuit