SLA4028 - High Density Gate Array

This page provides the datasheet information for the SLA4028, a member of the SLA4028SeikoEpsonCorp High Density Gate Array family.

Product Overview

Seiko Epson Corp

Part number	SLA4028
Manufacturer	Seiko Epson Corp
File Size	34.13 KB
Description	High Density Gate Array
Datasheet	SLA4028 Datasheet
Additional preview pages of the SLA4028 datasheet.

q q q q q Super-high density (adopting 0.45µm silicon gate CMOS with 2- and 3-metal layers) High-speed operation (operation delay of internal gate = 0.160ns at 3.3V, 2-input power NAND standard) Internal gate = 3.3 and 3.0V (2.0V single), I/O buffer = 5.0, 3.3 and 3.0V (2.0V single) (built-in level shifter) Low power consumption (0.80µW/MHz/BC when internal cell = 3.0V) Output drivability (IOL = 100µ, 1, 3, 6, 12, 24 mA when PCI = 5.0V, IOL = 100µ, 1, 2, 6, 12mA when PCI = 3.3V, IOL = 50µ, 300µ,.

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Published: Apr 4, 2005 |