Description
Connection pin of charge control FET gate (Pch open-drain output) Voltage detection pin between VDD pin and VMP pin Connection pin of discharge control FET gate (CMOS output) Voltage detection pin between VSS pin and VINI pin, discharge overcurrent 1 / 2 detection pin, load short-circuit detection p
Features
- High-accuracy voltage detection function for each cell
Overcharge detection voltage n (n = 1 to 4) Overcharge release voltage n (n = 1 to 4)
3.65 V to 4.6 V (50 mV step) 3.5 V to 4.6 V.
- 1
Accuracy ±25 mV Accuracy ±50 mV
Overdischarge detection voltage n (n = 1 to 4) Overdischarge release voltage n (n = 1 to 4)
2.0 V to 3.0 V (100 mV step) 2.0 V to 3.4 V.
- 2
Accuracy ±80 mV Accuracy ±100 mV.
- Discharge overcurrent detection in 3-step
Discharge overcurrent detectio.