ACS8525A Datasheet | SEMTECH

ACS8525A LC/P Line Card Protection Switch for SONET/SDH Systems MUNICATIONS ADVANCED MS & SENSING .. Description FINAL Features The ACS8525A is a highly integrated, single-chip solution for “Hit-less” protection switching of SEC (SDH/SONET Equipment Clock) + Sync clock “Groups”, from Master and Slave SETS clock cards and a third (Stand-by) source, for Line Cards in a SONET or SDH Network Element. The ACS8525A has fast activity monitors on the SEC clock inputs and will implement automatic system protection switching against the Master clock failure. The selection of the Master/Slave input can be forced by a Force Fast Switch pin. If both the Master and Slave input clocks fail, the Stand-by “Group” is selected or, if no Stand-by is available, the device enters Digital Holdover mode. The ACS8525A can perform frequency translation, converting, for example, an 8 k Hz SEC input clock from a backplane into a 155.52 MHz clock for local line cards. Master and Slave SEC inputs to the device support TTL/CMOS and PECL/LVDS. The Stand-by SEC and three Sync inputs are TTL/CMOS only. The ACS8525A generates two SEC clock outputs, via one PECL/LVDS and one TTL/CMOS port, with spot frequencies from 2 k Hz up to 311.04 MHz (up to 155.52 MHz on the TTL/CMOS port). It also provides an 8 k Hz Frame Sync and a 2 k Hz Multi-Frame Sync signal output with programmable pulse width and polarity. The ACS8525 includes a Serial Port, which can be SPI patible, providing access to the configuration and status registers for device setup. IEEE 1149.1 JTAG Boundary Scan is supported. Block Diagram Figure 1 Block Diagram of the ACS8525A LC/P 3 x SEC/Sync Input Groups SEC1 & SEC2: TTL/PECL/LVDS, SEC3 and all Syncs TTL only SEC1 Master SYNC1 SEC2 Slave SYNC2 SEC3 Stand-by SYNC3 SEC Inputs: Programmable Frequencies 2 k Hz, 4 k Hz, TCK N x 8 k Hz TDI 1.544/2.048 MHz TMS 6.48 MHz TRST 19.44 MHz TDO 25.92 MHz 38.88 MHz 51.84 MHz 77.76 MHz 155.52 MHz ‹ SONET/SDH...