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SC2597 - Low Voltage DDR Termination Regulator

General Description

The SC2597 is designed to meet the latest JEDEC specification for low power DDR3 and DDR4, while also supporting DDR and DDR2.

The SC2597 regulates up to + 3A for VTT and up to + 40mA for VREF.

Key Features

  • Input to linear regulator (VIN): 1.0V to 3.6V.
  • Output (VTT): 0.5V to 1.8V.
  • Bias Voltage (VDD): 2.35V to 3.6V.
  • Up to 3A sink or source from VTT for DDR through DDR4.
  • + 1% over temperature (with respect to VDDQ/2, in- cluding internal resistor divider variation) VREF and VTT.
  • Logic-level enable input.
  • Built in soft-start.
  • Thermal shutdown with auto-restar.

📥 Download Datasheet

Datasheet Details

Part number SC2597
Manufacturer SEMTECH
File Size 1.53 MB
Description Low Voltage DDR Termination Regulator
Datasheet download datasheet SC2597 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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POWER MANAGEMENT Features „„ Input to linear regulator (VIN): 1.0V to 3.6V „„ Output (VTT): 0.5V to 1.8V „„ Bias Voltage (VDD): 2.35V to 3.6V „„ Up to 3A sink or source from VTT for DDR through DDR4 „„ + 1% over temperature (with respect to VDDQ/2, in- cluding internal resistor divider variation) VREF and VTT „„ Logic-level enable input „„ Built in soft-start „„ Thermal shutdown with auto-restart „„ Over current protection „„ Minimal output capacitance „„ Package: SOIC8-EDP Applications „„ DDR Memory Termination SC2597 Low Voltage DDR Termination Regulator Description The SC2597 is designed to meet the latest JEDEC specification for low power DDR3 and DDR4, while also supporting DDR and DDR2. The SC2597 regulates up to + 3A for VTT and up to + 40mA for VREF.