Description
6
DEVICE OPERATION 7
THE VCO PLL BLOCK 7 THE OUTPUT DIVIDER BLOCK8 THE OUTPUT STAGE 8 THE CONTROL BLOCK 8
Reset9
USING THE ACS1790T 9
HARDWARE DEVICE CONFIGURATION9 Input clock frequency selection 9 Default output frequency selection 10
REGISTER-BASED DEVICE CONFIGURATION 10 I2C slave address select
Features
- Optimised for Synchronous Ethernet, SONET and SDH operation.
- Meets RMS jitter requirements of Gigabit Ethernet, 10 Gigabit Ethernet and OC-48 / STM16.
- Default options for 25 MHz & 125 MHz or 25 MHz & 156.25 MHz outputs at reset.
- High frequency LVPECL output: 10 MHz.
- 200 MHz, 1 ppb step.
- Low frequency LVCMOS output: 2 kHz.
- 125 MHz 1.8V, 2.5V and 3.3V operation.
- Very-low frequency feedback clock output for connection to ToPSync® or external PFD.
ACS1790T Datasheet
