PM8032 Datasheet | SEMTECH

Features an 8-lane native PCI-Express Gen-II link, enabling full-duplex operation simultaneously on all ports. The Tachyon QE8 is an integrated single chip solution ideal for a variety of high-performance I/O applications. The proven Tachyon State-Machine architecture scales directly with system CPU performance and is not limited by the constraints of an embedded microprocessor. The Tachyon QE8 supports up to 4 processors per FC link using 4 independent register and API queue structures. This feature allows systems to scale to required performance as necessary while maintaining patibility with the Tachyon programming model at the register level, and with the Tachyon Software Development Kit (TSDK) API tools. The Tachyon QE8 supports the Protection Information model as described in the SCSI Block mands - 2 (SBC-2) Standard, which incorporates a Data Integrity Field (DIF) in data records. Additionally, the QE8 has masking capabilities for enhanced functionality. T10 DIF provides robust CRC-based data protection with mechanisms to initiate, extend, verify and replace, or terminate a protection domain. The Tachyon QE8 offers additional performance by providing Multi-DMA and advanced frame-handling functions that are normally handled by the host processor. These enhancements make it possible for the system to utilize intelligent frame handling while reducing CPU utilization, memory controller utilization, and PCI-Express utilization. - ERQ/SCSI LL priority control for additional Quality of Service control - TWI control and presence detect for optical transceivers - Platform-independent software development API tools including sample code for Linux, and Windows - Standard and Ro HS pliant packages - Industry-leading technical support and documentation DATA INTEGRITY Features - Variable block size support: 512/520 - I/O level T10 DIF support - CRC Offload Engine (COE) - T10 DIF per L/A (DPL) TACHYON EXPRESSWAY ARCHITECTURE - Provides an interface from the Fibre Channel...