RClamp0524PA Datasheet | SEMTECH

Ultra Low Capacitance T VS Arrays PROTECTION PRODUCTS - Rail Clamp® Description Rail Clamp® T VS arrays are ultra lo w capacitance ESD protection devices designed to protect high speed data interfaces. This series has been specifically designed to protect sensitive ponents which are connected to high-speed data and transmission lines from overvoltage caused by ESD (electrostatic discharge), CDE (Cable Discharge Events), and EFT (electrical fast transients). The RClamp®0522PA and R Clamp®0524PA have a typical capacitance of only 0.30p F between I/O pins. This allows it to be used on circuits operating in excess of 3GHz without signal attenuation. They may be used to meet the ESD immunity req uirements of IEC 6 10004-2. The R Clamp0522PA is designed t o protect two lines, while the R Clamp0524PA will pr otect four lines. The R Clamp0522PA is in a 6-pin SLP1 610P4 pack age. It measures 1.6 x 1.0 with a nominal height of 0.58mm. The RClamp0524PA is in a 1 0-pin SLP2510P8 package. It measures 2.5 x 1.0 with a nominal height of 0.58mm. The leads are spaced at a pitch of 0.5mm and are finished with lead-free Ni Pd Au. They are designed for easy PCB layout by allowing the traces to run straight through the device. The bination of small size, low capacitance, and high level of ESD protection makes them a flexible solution for applications such as HDMI, Display Port TM, MDDI, and e SA TA int erfaces. RClamp0522PA RClamp0524PA PRELIMINARY Features ‹ ESD protection for high-speed data lines to IEC 61000-4-2 (ESD) ±1 7k V (air), ±1 2k V (cont act) IEC 61000-4-5 (Lightning) 5A (8/20 μs) IEC 61000-4-4 (EFT) 40A (5/50ns) Package design optimized for high speed lines Flow-Through design Protects two or four I/O lines Low capacitance: 0.3p F typical (I/O to I/O) Low clamping voltage Low operating voltage: 5V Solid-state silicon-avalanche technology SLP1610P4 6-pin pack age (1.6 x 1 .0 x 0.58mm) SLP2510P8 10-pin package (2.5 x 1 .0 x 0.58mm) Pb-Free, Halogen F ree, R o HS/WEEE...