LH543611 - 512 x 36 x 2 / 1024 x 36 x 2 Synchronous Bidirectional FIFO
Sharp Corporation
General Description
The LH543611 and LH543621 contain two FIFO buffers, FIFO #1 and FIFO #2.
These operate in parallel, but in opposite directions, for bidirectional data buffering.
FIFO #1 and FIFO #2 each are organized as 512 or 1024 by 36 bits.
Key Features
Pin-Compatible and Functionally.
Upwards-Compatible with Sharp LH5420 and LH543601, but Deeper Expanded Control Register that is Fully Readable as well as Writeable Fast Cycle Times: 18/20/25/30/35 ns Improved Input Setup and Flag Out Timing.
Full PDF Text Transcription for LH543611 (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
LH543611. For precise diagrams, and layout, please refer to the original PDF.
LH543611/21 FEATURES • Pin-Compatible and Functionally • • • • • • • • • • • • • • • • • • • • • • • • • Upwards-Compatible with Sharp LH5420 and LH543601, but Deeper Exp...
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• • Upwards-Compatible with Sharp LH5420 and LH543601, but Deeper Expanded Control Register that is Fully Readable as well as Writeable Fast Cycle Times: 18/20/25/30/35 ns Improved Input Setup and Flag Out Timing Two 512 × 36-bit FIFO Buffers (LH543611) or Two 1024 × 36-bit FIFO Buffers (LH543621) Full 36-bit Word Width Selectable 36/18/9-bit Word Width on Port B; Selection May be Changed Without Resetting the BiFIFO Programmable Byte-Order Reversal – ‘Big-Endian ↔ Little-Endian Conversion’ Independently-Synchronized (‘Fully-Asynchronous’) Operation of Port A and Port B ‘Synchronous’ Enable-Plus-Clock Control at Both Port
LH543611 Datasheet
