LH5P832 Datasheet PDF - Sharp Electrionic Components CMOS 256K (32K x 8) Pseudo-Static RAM Specs

LH5P832 - CMOS 256K (32K x 8) Pseudo-Static RAM

Datasheet Summary

Description

The LH5P832 is a 256K bit Pseudo-Static RAM organized as 32,768 × 8 bits.

It is fabricated using silicon-gate CMOS process technology.

The LH5P832 uses convenient on-chip refresh circuitry with a DRAM memory cell for pseudo static operation.

Features

32,768 × 8 bit organization.
Access time: 100/120 ns (MAX. ).
Cycle time: 160/190 ns (MIN. ).
Power consumption: Operating: 357.5/303 mW Standby: 16.5 mW.
TTL compatible I/O.
256 refresh cycle/4 ms.
Auto refresh is executed by internal counter (controlled by OE/RFSH pin).
Self refresh is executed by internal timer.
Single +5 V power supply.
Packages: 28-pin, 600-mil DIP 28-pin, 300-mil SK-DIP 28-pin, 450-mil.

Datasheet Details

Part number	LH5P832
Manufacturer	Sharp Electrionic Components
File Size	95.47 KB
Description	CMOS 256K (32K x 8) Pseudo-Static RAM
Datasheet	LH5P832 Datasheet
Additional preview pages of the LH5P832 datasheet.

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Full PDF Text Transcription

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LH5P832 FEATURES • 32,768 × 8 bit organization • Access time: 100/120 ns (MAX.) • Cycle time: 160/190 ns (MIN.) • Power consumption: Operating: 357.5/303 mW Standby: 16.5 mW • TTL compatible I/O • 256 refresh cycle/4 ms • Auto refresh is executed by internal counter (controlled by OE/RFSH pin) • Self refresh is executed by internal timer • Single +5 V power supply • Packages: 28-pin, 600-mil DIP 28-pin, 300-mil SK-DIP 28-pin, 450-mil SOP DESCRIPTION The LH5P832 is a 256K bit Pseudo-Static RAM organized as 32,768 × 8 bits. It is fabricated using silicon-gate CMOS process technology. The LH5P832 uses convenient on-chip refresh circuitry with a DRAM memory cell for pseudo static operation.

Published: Mar 22, 2005 |