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LH5P860 - CMOS 512K (64K x 8) Pseudo-Static RAM

Datasheet Summary

Description

The LH5P860 is a 512K-bit Pseudo-Static RAM organized as 65,536 × 8 bits.

It is fabricated using silicon-gate CMOS process technology.

With its built-in oscillator, it is easy to refresh memories without an external clock.

Features

  • 65,536 × 8 bit organization.
  • Access time: 80 ns (MAX. ).
  • Cycle time: 140 ns (MIN. ).
  • Single +5 V power supply.
  • Pin compatible with 1M standard SRAM.
  • Power consumption (MAX. ): Operating: 440 mW Self refresh (TTL level): 5.5 mW Self refresh (CMOS level): 2.75 mW.
  • TTL compatible I/O.
  • 512 refresh cycles/8 ms (MAX. ).
  • Available for auto-refresh and self-refresh modes.
  • Packages: 32-pin, 600-mil DIP 32-pin, 525-mil.

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Datasheet Details

Part number LH5P860
Manufacturer Sharp Electrionic Components
File Size 108.35 KB
Description CMOS 512K (64K x 8) Pseudo-Static RAM
Datasheet download datasheet LH5P860 Datasheet
Additional preview pages of the LH5P860 datasheet.

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LH5P860 FEATURES • 65,536 × 8 bit organization • Access time: 80 ns (MAX.) • Cycle time: 140 ns (MIN.) • Single +5 V power supply • Pin compatible with 1M standard SRAM • Power consumption (MAX.): Operating: 440 mW Self refresh (TTL level): 5.5 mW Self refresh (CMOS level): 2.75 mW • TTL compatible I/O • 512 refresh cycles/8 ms (MAX.) • Available for auto-refresh and self-refresh modes • Packages: 32-pin, 600-mil DIP 32-pin, 525-mil SOP CMOS 512K (64K × 8) Pseudo-Static RAM DESCRIPTION The LH5P860 is a 512K-bit Pseudo-Static RAM organized as 65,536 × 8 bits. It is fabricated using silicon-gate CMOS process technology. With its built-in oscillator, it is easy to refresh memories without an external clock.
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