SM6010

SM6010 Key Features

• General purpose registers 16-bit × 16
• 62 basic instruction (bit manipulation instructions suitable for controlling, bit transfer instructions, bit branch inst
• 10 addressing modes
• 16M of address space
• An interrupt request starts a high performance automatic data transfer (DTS). Appropriate settings of interrupts and reg
• System clock cycle
• 0.133 µs MIN. (VDD = 4.5 V to 5.5 V at 30 MHz main clock cycle)
• 0.2 µs MIN. (VDD = 2.7 V to 5.5 V, at 20 MHz main clock cycle)
• Selectable system clocks divided by 2 up to 16 main clocks for low power operation
• Memory interface