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LH51BV1000J Datasheet PDF

Sharp LH51BV1000J

The LH51BV1000JY is a static RAM organized as 131,072 × 8 bits which provides low power standby mode. It is fabricated using silicon-gate CMOS process technology.
Part No. LH51BV1000J
Datasheet LH51BV1000J Download
Manufacturer
Sharp
Description CMOS 1M (128K x 8) Static Ram
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LH51BV1000J datasheet page 1 preview

FEATURES

● Access time: 70 ns (MAX.)
● Current consumption: Operating: 30 mA (MAX.) 5 mA (MAX.) (tRC, tWC = 1 µs) Standby: 60 µA (MAX.)
● Data Retention: 1.0 µA (MAX.) (VCCDR = 3 V, TA = 25°C)
● Single power supply: 2.7 V to 3.6 V
● Operating temperature: -25°C to +85°C
● Fully-static operation
● Three-state output
● Not designed or rated as radiation hardened
● Package: 32-pin 6 × 10 mm CSP
● N-type bulk silicon

DESCRIPTION

A B C D E F CMOS 1M (128K × 8) Static Ram PIN CONNECTIONS 1 A2 I/O1 GND I/O4 I/O7 A10 2 A3 A0 I/O3 I/O5 3 A1 I/O2 4 5 6 NC A12 7 A4 A6 A14 A15 8 A5 A7 A16 VCC WE A9 I/O8 I/O6 OE CE1 CE2 A8 A13 A11 51BV1000-1 Figure 1. Pin Connections for CSP Package 1 LH51BV1000J CMOS 1M (128K × 8) Static RAM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 ADDRESS BUFFER VCC GND 10 1024 ROW DECODER MEMORY CELL ARRAY (1024 x 128 x 8) 128 x 8 7 COLUMN DECODER 128 COLUMN GATE 8 CE1, CE2 CONTROL LOGIC CE1 CE2 WE OE OE, WE CONTROL LOGIC I/O BUFFER I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 51BV1000-2 Figure 2.
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