Sharp LH521028
The LH521028 is a high-speed 1,179,648-bit CMOS SRAM organized as 64K × 18. The LH521028 is available in a compact 52-Pin PLCC, which along with the six pairs of supply terminals, provide for reliable operation. The control signals include Write Enable (W), Chip Enable (E), High and Low Byte Select (S L and SH), Output Enable (G) and Address Latch Enable (ALE).| Part No. | LH521028 |
|---|---|
| Datasheet | LH521028 Download |
| Manufacturer |  Sharp |
| Description | CMOS 64K x 18 Static RAM |
| Buy | Stock & Price |
FEATURES
● Fast Access Times: 17/20/25/35 ns● Wide Word (18-Bits) for: – Improved Performance – Reduced Component Count – Nine-bit Byte for Parity
● Transparent Address Latch
● Reduced Loading on Address Bus
● Low-Power Stand-by Mode when Deselected
● TTL Compatible I/O
● 5 V ± 10% Supply
● 2 V Data Retention
● JEDEC Standard Pinout
● Package: 52-Pin PLCC 52-PIN PLCC CMOS 64K × 18 Static RAM operations on the high and the low bytes. The Address Latches are transparent when ALE is HIGH (for applications not requiring a latch), and are latched when ALE is LOW. The Address Latches and the wide word help to eliminate the need for external Address busbuffers and/or latches. Write cycles occur when Chip Enable (E), SH and/or SL, and Write Enable (W) are LOW. The Byte-select signals can be used for Byte-write operations by disabling the other byte during the Write operation. Data is transferred from the DQ pins to the memory location specified by the 16 address lines. The proper use of the Output Enable control (G) can prevent bus contention.
