Sharp LH5268A
The LH5268A is a static RAM organized as 8,192 × 8 bits. It is fabricated using silicon-gate CMOS process technology.| Part No. | LH5268A |
|---|---|
| Datasheet | LH5268A Download |
| Manufacturer |  Sharp |
| Description | CMOS 64K (8K x 8) Static RAM |
| Buy | Stock & Price |
FEATURES
● 8,192 × 8 bit organization● Access time: 100 ns (MAX.)
● Power consumption: Operating: 220 mW (MAX.) 55 mW (MAX.) (tRC, tWC = 1 µs) Standby: 220 µW (MAX.) Data retention: 3.0 µW (VCC = 3 V, TA = 25 °C)
● Fully-static operation
● Three-state outputs
● Single +5 V power supply
● TTL compatible I/O
● Packages: 28-pin, 600-mil DIP 28-pin, 300-mil SK-DIP 28-pin, 450-mil SOP CMOS 64K (8K × 8) Static RAM
DESCRIPTION
PIN CONNECTIONS 28-PIN DIP 28-PIN SK-DIP 28-PIN SOP NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE CE2 A8 A9 A11 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 5268A-1 TOP VIEW Figure 1. Pin Connections for DIP, SK-DIP, and SOP Packages 1 LH5268A CMOS 64K (8K × 8) Static RAM ROW DECODERS ROW ADDRESS BUFFER A12 2 A8 25 A7 3 A6 4 A5 5 A4 6 A3 7 MEMORY ARRAY (128 x 512) 28 VCC 14 GND I/O1 I/O2 I/O3 I/O4 11 12 13 15 I/O CIRCUITS DATA CONTROL COLUMN DECODER I/O5 16 I/O6 17 I/O7 18 I/O8 19 COLUMN ADDRESS BUFFER WE 27 OE 22 CE2 26 CE1 20 23 24 21 8 10 9 A11A9 A10 A2 A0 A1 5268A-2 Figure 2.
