Sharp LH532100B
The LH532100B is a 2M-bit mask-programmable ROM organized as 262,144 × 8 bits. It is fabricated using silicon-gate CMOS process technology.| Part No. | LH532100B |
|---|---|
| Datasheet | LH532100B Download |
| Manufacturer |  Sharp |
| Description | CMOS 2M (256K x 8) MROM |
| Buy | Stock & Price |
FEATURES
● 262,144 words × 8 bit organization● Access time: 150 ns (MAX.)
● Low-power consumption: Operating: 275 mW (MAX.) Standby: 550 µW (MAX.)
● Static operation
● Mask-programmable OE/OE and OE1/OE1/DC
● TTL compatible I/O
● Three-state outputs
● Single +5 V power supply
● Packages: 32-pin, 600-mil DIP 32-pin, 525-mil SOP 32-pin, 450-mil QFJ (PLCC) 32-pin, 8 × 20 mm2 TSOP (Type I) 32-pin, 400-mil TSOP (Type II)
● JEDEC standard EPROM pinout (DIP) CMOS 2M (256K × 8) MROM
DESCRIPTION
PIN CONNECTIONS 32-PIN DIP 32-PIN SOP OE1/OE1/DC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC DC A17 A14 A13 A8 A9 A11 OE/OE A10 CE D7 D6 D5 D4 D3 532100B-1 TOP VIEW Figure 1. Pin Connections for DIP and SOP Packages GND 32-PIN QFJ D6 D5 D4 D3 TOP VIEW D2 D1 20 19 18 17 16 15 14 D7 CE A10 OE/OE A11 A9 A8 A13 A14 21 22 23 24 25 26 27 28 29 30 31 32 VCC DC A17 13 12 11 10 9 8 7 6 5 1 OE1/OE1/DC D0 A0 A1 A2 A3 A4 A5 A6 A7 2 A16 3 A15 4 A12 532100B-7 Figure 2.
