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LH540215 Datasheet PDF

Sharp LH540215

the LH540215/25 FIFOs in IDT-Compatible Operating Mode may skip over BOLD ITALIC sections, if they wish. The LH540215/25 parts are FIFO (First-In, First-Out) memory devices, based on fully-static CMOS dual-port SRAM technology, capable of containing up to 512 or 1024 18-bit words respectively. They can replace two or more byte-wide FIFOs in many applications, for microprocessorto-microprocessor or microprocessor-to-bus communication.
Part No. LH540215
Datasheet LH540215 Download
Manufacturer
Sharp
Description 512 x 18 / 1024 x 18 Synchronous FIFO
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LH540215 datasheet page 1 preview

FEATURES

● Fast Cycle Times: 20/25/35 ns
● Pin-Compatible Drop-In Replacements for IDT72215B/25B FIFOs 512 × 18 / 1024 × 18 Synchronous FIFO
● May be Cascaded for Increased Depth, or Paralleled for Increased Width
● Five Status Flags: Full, Almost-Full, Half-Full, Almost-Empty, and Empty; ‘Almost’ Flags are Programmable
● Choice of IDT-Compatible or Enhanced Operating Mode; Selected by an Input Control Signal
● In Enhanced Operating Mode, Almost-Full, Half-Full, and Almost-Empty Flags can be Made Completely Synchronous
● Device Comes Up into One of Two Known Default States at Reset Depending on the State of the EMODE Control Input: Programming is Allowed, but is not Required
● In Enhanced Operating Mode, Duplicate Enables for Interlocked Paralleled FIFO Operation, for 36-Bit Data Width, when Selected and Appropriately Connected
● Internal Memory Array Architecture Based on CMOS Dual-Port SRAM Technology, 512 × 18 or 1024 × 18 Input Port and Output Port
● ‘Synchronous’ Enable-Plus-Clock...
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