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LH5P8129 Datasheet PDF

Sharp LH5P8129

The LH5P8129 is a 1M bit Pseudo-Static RAM organized as 131,072 × 8 bits. It is fabricated using silicon-gate CMOS process technology. The advantage is the cost savings realized with the lower cost PSRAM.
Part No. LH5P8129
Datasheet LH5P8129 Download
Manufacturer
Sharp
Description CMOS 1M (128K x 8) CS-Control Pseudo-Static RAM
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LH5P8129 datasheet page 1 preview

FEATURES

● 131,072 × 8 bit organization
● Access times (MAX.): 60/80/100 ns
● Cycle times (MIN.): 100/130/160 ns
● Single +5 V power supply
● Pin compatible with 1M standard SRAM
● Power consumption: Operating: 572/385/275 mW (MAX.) Standby (TTL level): 5.5 mW (MAX.) Standby (CMOS level): 1.1 mW (MAX.)
● TTL compatible I/O
● Available for auto-refresh and self-refresh modes
● 512 refresh cycles/8 ms
● Packages: 32-pin, 600-mil DIP 32-pin, 525-mil SOP 32-pin, 8 × 20 mm2 TSOP (Type I)

DESCRIPTION

A PSRAM uses on-chip refresh circuitry with a DRAM memory cell for pseudo static operation which eliminates external clock inputs, while considering the pinout compatibility with industry standard SRAMs. The LH5P8129 PSRAM has a built-in oscillator, which makes it easy to refresh memories without external clocks. CMOS 1M (128K × 8) CS-Control Pseudo-Static RAM PIN CONNECTIONS 32-PIN DIP 32-PIN SOP RFSH A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CS R/W A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 5P8129-1 TOP VIEW Figure 1.
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