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HYB3117400BJ-70 - 3.3V 4M x 4-Bit Dynamic RAM

General Description

DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns)

Key Features

  • include single + 3.3 V (± 0.3 V) power supply, direct interfacing with high-performance logic device families. The HYB3116400BTL parts have a very low power „sleep mode“ supported by Self Refresh. Ordering Information Type HYB 3117400BJ-50 HYB 3117400BJ-60 HYB 3117400BJ-70 HYB 3117400BT-50 HYB 3117400BT-60 HYB 3117400BT-70 HYB 3116400BJ-50 HYB 3116400BJ-60 HYB 3116400BJ-70 HYB 3116400BT-50 HYB 3116400BT-60 HYB 3116400BT-70 HYB 3116400BTL-50 HYB 3116400BTL-60 HYB 3116400BTL-70 Ordering Code Pac.

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Full PDF Text Transcription for HYB3117400BJ-70 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for HYB3117400BJ-70. For precise diagrams, and layout, please refer to the original PDF.

3.3V 4M x 4-Bit Dynamic RAM HYB3116400BJ/BT(L) -50/-60/-70 HYB3117400BJ/BT(L) -50/-60/-70 Advanced Information • • • 4 194 304 words by 4-bit organization 0 to 70 °C oper...

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nformation • • • 4 194 304 words by 4-bit organization 0 to 70 °C operating temperature Performance: -50 tRAC tCAC tAA tRC tPC RAS access time CAS access time Access time from address Read/Write cycle time Fast page mode cycle time 50 13 25 90 35 -60 60 15 30 110 40 -70 70 20 35 130 45 ns ns ns ns ns • • • • • • • • Single + 3.3 V (± 0.3V ) supply Low power dissipation max. 396 active mW (HYB3117400BJ/BT-50) max. 363 active mW (HYB3117400BJ/BT-60) max. 330 active mW (HYB3117400BJ/BT-70) max. 360 active mW (HYB3116400BJ/BT-50) max. 324 active mW (HYB3116400BJ/BT-60) max. 288 active mW (HYB3116400BJ/BT-70) 7.2 mW standby (LV

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