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HYB3117405BJ-60 - 4M x 4-Bit Dynamic RAM 2k & 4k Refresh

General Description

DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns)

Key Features

  • include single + 3.3 V (± 0.3 V) power supply, direct interfacing with high-performance logic device families. The HYB3116405BTL parts have a very low power „sleep mode“ supported by Self Refresh. Ordering Information Type HYB 3117405BJ-50 HYB 3117405BJ-60 HYB 3117405BJ-70 HYB 3117405BT-50 HYB 3117405BT-60 HYB 3117405BT-70 HYB 3116405BJ-50 HYB 3116405BJ-60 HYB 3116405BJ-70 HYB 3116405BT-50 HYB 3116405BT-60 HYB 3116405BT-70 HYB 3116405BTL-50 HYB 3116405BTL-60 HYB 3116405BTL-70 Q67100-Q1143 Q67100.

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Full PDF Text Transcription for HYB3117405BJ-60 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for HYB3117405BJ-60. For precise diagrams, and layout, please refer to the original PDF.

3.3V 4M x 4-Bit EDO-Dynamic RAM HYB3116405BJ/BT(L) -50/-60/-70 HYB3117405BJ/BT(L) -50/-60/-70 Advanced Information • • • 4 194 304 words by 4-bit organization 0 to 70 °C ...

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ed Information • • • 4 194 304 words by 4-bit organization 0 to 70 °C operating temperature Performance -50 tRAC tCAC tAA tRC tHPC RAS access time CAS access time Access time from address Read/Write cycle time Hyper page mode (EDO) cycle time 50 13 25 84 20 -60 60 15 30 104 25 -70 70 20 35 124 30 ns ns ns ns ns • • • • • • • • Single + 3.3 V (± 0.3V ) supply Low power dissipation max. 396 active mW (HYB3117405BJ/BT-50) max. 363 active mW (HYB3117405BJ/BT-60) max. 330 active mW (HYB3117405BJ/BT-70) max. 360 active mW (HYB3116405BJ/BT-50) max. 324 active mW (HYB3116405BJ/BT-60) max. 288 active mW (HYB3116405BJ/BT-70) 7.2 mW

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