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HYB3117805BSJ-50 - 2M x 8-Bit Dynamic RAM 2k Refresh

General Description

5V 5V 50 ns EDO-DRAM 60 ns EDO-DRAM 3.3 V 50 ns EDO-DRAM 3.3 V 60 ns EDO-DRAM Pin Names and Configuration A0 - A10 A0 - A9 RAS OE I/O1 - I/O8 CAS WE Row Address Inputs Column Address Inputs Row Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply + 5

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Full PDF Text Transcription for HYB3117805BSJ-50 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for HYB3117805BSJ-50. For precise diagrams, and layout, please refer to the original PDF.

2M × 8-Bit Dynamic RAM 2k Refresh (Hyper Page Mode-EDO) Advanced Information • 2 097 152 words by 8-bit organization • 0 to 70 °C operating temperature • Hyper Page Mode-...

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bit organization • 0 to 70 °C operating temperature • Hyper Page Mode-EDO-operation • Performance: -50 -60 60 15 30 104 25 HYB 5117805/BSJ-50/-60 HYB 3117805/BSJ-50/-60 tRAC tCAC tAA tRC tHPC RAS access time CAS access time Access time from address Read/Write cycle time Hyper page mode (EDO) cycle time 50 13 25 84 20 ns ns ns ns ns • Power dissipation: HYB 5117805 -50 Power Supply Active TTL Standby CMOS Standby 440 11 5.5 -60 385 5 ± 10% HYB 3117805 -50 288 7.2 3.6 -60 252 mW mW mW 3.3 ± 0.3 V • Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh and test mode • All inputs, outputs and

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