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PEB22320 - Primary Rate Access Clock Generator and Transceiver

General Description

are fulfilled.

Table of Contents 1 1.1 1.2 1.3 2 2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.2 2.2.1 2.2.2 2.3 2.4 2.5 2.6 2.7 2.

Key Features

  • . . .5 Pin Configuration (top view).
  • . . . .7 Pin Definitions and Functions.
  • . . .8 System Integration.
  • . . . . .10 Functional.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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ICs for Communications Primary Rate Access Clock Generator and Transceiver PRACT PEB 22320 Version 2.1 Data Sheet 04.95 PEB 22320 Revision History Previous Version: Page 10 14 16 17 18 23 24 28 29 31 32, 33 Current Version: 04.95 05.93 Subjects (changes since last revision) Architecture of the PRACT Input Jitter Specification Jitter Attenuator Block Diagram Clock- and Synchronization Table Jitter Attenuation Characteristics Master/Slave Selection Reset Delay Times DC Characteristics Recommended Oscillator Circuits Crystal Tuning Range Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.