SAF-C501G-1EN
description for ALE/PROG and EA/Vpp pleted Port 1, 3, 2 pin description
: “bidirectional” replaced by “quasibidirectional” Block diagram updated for C501G-1E New design of register (PSW) description
“Memory organization” added Actualized design of the SFR tables Reset value of T2CON corrected Description for the C501-1E OTP version added DC characteristics for C501-1E added Timing “External Clock Drive” now behind “Data Memory Cycle” AC characteristics for C501-1E added
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