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HYB39S64160AT - 64M-Bit Synchronous DRAM

Download the HYB39S64160AT datasheet PDF. This datasheet also covers the HYB39S64400 variant, as both devices belong to the same 64m-bit synchronous dram family and are provided as variant models within a single manufacturer datasheet.

General Description

LVTTL-version: HYB 39S64400AT-8 HYB 39S64400AT-8B HYB 39S64400AT-10 HYB 39S64800AT-8 HYB 39S64800AT-8B HYB 39S64800AT-10 HYB 39S64160AT-8 HYB 39S64160AT-8B HYB 39S64160AT-10 HYB 39S64xxx0ATL-8/-10 P-TSOP-54-2 (400mil) P-TSOP-54-2 (400mil) P-TSOP-54-2 (400mil) P-TSOP-54-2 (400mil) P-TSOP-54-2 (400mi

Key Features

  • Mode Register Set (MRS) No Operation (NOP) Device Deselect (INHBT) Auto Refresh (REFA) Self Refresh Entry (REFS-EN) Self Refresh Exit (REFS-E.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HYB39S64400_SiemensSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
HYB39S64160BT 64-MBit Synchronous DRAM Infineon Technologies
HYB39S64160BTL 64-MBit Synchronous DRAM Infineon Technologies
HYB39S64400BT 64-MBit Synchronous DRAM Infineon Technologies
HYB39S64400BTL 64-MBit Synchronous DRAM Infineon Technologies
HYB39S64800BT 64-MBit Synchronous DRAM Infineon Technologies

Other Datasheets by Siemens Semiconductor Group (now Infineon)

Part Number Description
HYB39S64400 64M-Bit Synchronous DRAM
HYB39S64800 64M-Bit Synchronous DRAM
HYB39S13620TQ-6 Special Mode Registers Two color registers Burst Read
HYB39S13620TQ-7 Special Mode Registers Two color registers Burst Read
HYB39S13620TQ-8 Special Mode Registers Two color registers Burst Read

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM 64 MBit Synchronous DRAM • High Performance: -8 fCKmax. tCK3 tAC3 tCK2 tAC2 125 8 6 10 6 -8B 100 10 6 12 7 -10 100 10 7 15 8 Units MHz ns ns ns ns • • • • • • • • • • • • Multiple Burst Read with Single Write Operation Automatic Command and Controlled Precharge Data Mask for Read / Write control (x4, x8) Data Mask for byte control (x16) Auto Refresh (CBR) and Self Refresh Suspend Mode and Power Down Mode 4096 refresh cycles / 64 ms Random Column Address every CLK ( 1-N Rule) Single 3.3V +/- 0.