SAE81C52 Datasheet | Siemens Semiconductor Group

256 x 8-Bit Static CMOS RAM NMOS-patible Preliminary Data CMOS IC PFeatures q 256 .. q q SAE 81C52 q q q q q x 8-bit organization Standby mode patible with the NMOS and CMOS versions of the microprocessor/microcontroller families SAB 8086, SAB 8051 Very low power dissipation Data retention up to VDD ≥ 1 V Three different chip select inputs for two chip select modes No increasing power consumption in standby mode if the control inputs are on undefined potential Temperature range - 40 to 110 °C P-DIP-16-1 P-DSO-20-1 Type SAE 81C52 P SAE 81C52 G Ordering Code Q67100-H9017 Q67100-H9015 Package P-DIP-16-1 P-DSO-20-1 (SMD) The SAE 81C52 is a CMOS-silicon gate, static random access memory (RAM), organized as 256 words by 8 bits. The multiplexed address and data bus interfaces directly to 8-bit microprocessors/microcontrollers without any timing or level problems, e.g. the families SAB 8086, SAB 8051. All inputs and outputs are fully patible with NMOS circuits, except CS1. Data retention is ensured up to VDD ≥ 1.0 V. The SAE 81C52 has three different inputs for two chip select modes which allow to inhibit either the address/data lines (AD 0 … AD 7) and the control lines (WR, RD, ALE, CS2, CS3), or only the control lines RD, WR. The power consumption is max. 5.5 µW in standby mode and max. 16.5 m W in operation. In standby mode, the power consumption will not increase if the control inputs are on undefined potential. Semiconductor Group 1 09.94 SAE 81C52 Pin Configurations (top view) SAE 81C52 P SAE 81C52 G .. Semiconductor Group SAE 81C52 Pin Definitions and Functions SAE 81C52 G Pin No. 1, 2, 4, 5, 6 7, 12, 14 .. SAE 81C52 P Pin No. 1…6 10, 11 12 Symbol Function AD0 … 7 CS1 Address/data lines Chip select 1 (standby) active low; inhibits all lines including control lines Address latch enable Write enable Read enable Power supply GND (0 V) Chip select 2; inhibits control inputs RD, WR Counterpart to CS2 16 17 19 20 9 10 11 13 14 15 16 7 8 9 ALE WR...