FEATURES
q q q Short-circuit shutdown with clock generator Four driver circuits for controlling power transistors Overload and short-circuit signaling P-DIP-18-1 Type FZL 4145 D GENERAL DESCRIPTION
Ordering Code Q67000-H8437 Package P-DIP-18-1 The input threshold can be adjusted between 1.5 V and 7 V. Overload or shortcircuit failure at an output will be indicated at pin SQ (signaling output). Functional DESCRIPTION
Each driver circuit has one active high driver input Dl and a common enable input (ENA) (active high) is provided for all stages. The (Q) outputs are designed to drive the output transistors. The load current is sampled via pin W. If the load current exceeds the preset value, the output stage switches off. Switching-on again is provided by the built-in clock generator. Its operation requires an external capacitor CT at pin C. If CT is bridged by a break-key, switching on can only be carried out by operating a key. The duty cycle of the clock generator is 1:50 (e.g. 40 µs/2 ms with CT = 33 nF).
Siemens
