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HYB5117805BJ-50 - 2M x 8 - Bit Dynamic RAM 2k Refresh

General Description

N.C.

VCC I/O1 I/O2 I/O3 I/O4 WE RAS N.C.

Key Features

  • include single + 5 V (± 10 %) power supply, direct interfacing with high-performance logic device families such as Schottky TTL. Ordering Information Type HYB 5117805BJ-50 HYB 5117805BJ-60 HYB 5117805BJ-70 Pin Names A0-A10 A0-A9 RAS OE I/O1-I/O8 CAS WE Row Address Inputs Column Address Inputs Row Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply (+ 5 V) Ground (0 V) not connected Ordering Code Q67100-Q1104 Q67100-Q1105 Q67100-Q1106 Package P-SOJ-2.

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Full PDF Text Transcription for HYB5117805BJ-50 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for HYB5117805BJ-50. For precise diagrams, and layout, please refer to the original PDF.

2M x 8 - Bit Dynamic RAM 2k Refresh (Hyper Page Mode- EDO) Advanced Information • • • HYB5117805BSJ -50/-60/-70 2 097 152 words by 8-bit organization 0 to 70 °C operating...

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-50/-60/-70 2 097 152 words by 8-bit organization 0 to 70 °C operating temperature Performance: -50 tRAC tCAC tAA tRC tHPC RAS access time CAS access time Access time from address Read/Write cycle time Hyper page mode (EDO) cycle time 50 13 25 84 20 -60 60 15 30 104 25 -70 70 20 35 124 30 ns ns ns ns ns • • Single + 5 V (± 10 %) supply Low power dissipation max. 660 mW active (-50 version) max. 605 mW active (-60 version) max. 550 mW active (-70 version) 11 mW standby (TTL) 5.5.

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