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HYM322030GS-70 - 2M x 32-Bit Dynamic RAM Module

Description

DRAM Module (access time 50 ns) DRAM Module (access time 60 ns) DRAM Module (access time 70 ns) DRAM Module (access time 50 ns) DRAM Module (access time 60 ns) DRAM Module (access time 70 ns) Semiconductor Group 2 HYM 322030S/GS-50/-60/-70 2M × 32-Bit Pin Configuration Pin Names VSS DQ16 DQ17 D

Features

  • which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT =.

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Full PDF Text Transcription

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2M x 32-Bit Dynamic RAM Module HYM 322030S/GS-50/-60/-70 Advanced Information • • • 2 097 152 words by 32-bit organization 1 memory bank Fast access and cycle time 50 ns access time 90 ns cycle time (-50 version) 60 ns access time 110 ns cycle time (-60 version) 70 ns access time 130 ns cycle time (-70 version) Fast page mode capability 35 ns cycle time (-50 version) 40 ns cycle time (-60 version) 45 ns cycle time (-70 version) Single + 5 V (± 10 %) supply Low power dissipation max. 2640 mW active (-50 version) max. 2420 mW active (-60 version) max.
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