DRAM Module (access time 60 ns) DRAM Module (access time 70 ns) DRAM Module (access time 60 ns) DRAM Module (access time 70 ns)
Semiconductor Group
601
05.94
HYM 362140S/GS-60/-70 2M x 36-Bit
The HYM 362140S/GS-60/-70 is a 8 M Byte DRAM module organized as 2 097 152 words by 36-bit in a 72-pin
Full PDF Text Transcription for HYM362140S (Reference)
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HYM362140S. For precise diagrams, and layout, please refer to the original PDF.
2M x 36-Bit Dynamic RAM Module HYM 362140S/GS-60/-70 Advanced Information • 2 097 152 words by 36-bit organization (alternative 4 194 304 words by 18-bit) Fast access and...
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t organization (alternative 4 194 304 words by 18-bit) Fast access and cycle time 60 ns access time 110 ns cycle time (-60 version) 70 ns access time 130 ns cycle time (-70 version) Fast page mode capability with 40 ns cycle time (-60 version) 45 ns cycle time (-70 version) Single + 5 V (± 10 %) supply Low power dissipation max. 6952 mW active (-60 version) max. 6292 mW active (-70 version) CMOS – 132 mW standby TTL – 264 mW standby • • CAS-before-RAS refresh RAS-only-refresh Hidden-refresh 12 decoupling capacitors mounted on substrate All inputs, outputs and clocks fully TTL compatible 72 pin Single in-Line Memory Module
More Datasheets from Siemens Semiconductor Group (now Infineon)
HYM362140S Datasheet
