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HYM364025GS-50 - 4M x 36-Bit EDO - DRAM Module

General Description

VSS DQ18 DQ19 DQ20 DQ21 N.C.

Key Features

  • d of 8 RAS cycles are required. 6) AC measurements assume.

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Full PDF Text Transcription for HYM364025GS-50 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for HYM364025GS-50. For precise diagrams, and layout, please refer to the original PDF.

4M x 36-Bit EDO - DRAM Module HYM364025S/GS-50/-60 • SIMM modules with 4 194 304 words by 36-Bit organization for PC main memory applications Fast access and cycle time 5...

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anization for PC main memory applications Fast access and cycle time 50 ns access time 84 ns cycle time (-50 version) 60 ns access time 104 ns cycle time (-60 version) Hyper Page Mode (EDO) capability 20 ns cycle time (-50 version) 25 ns cycle time (-60 version) Single + 5 V (± 10 %) supply Low power dissipation max. 6820 mW active (-50 version) max. 6160 mW active (-60 version) CMOS – 66 mW standby TTL –132 mW standby CAS-before-RAS refresh RAS-only-refresh Hidden-refresh Decoupling capacitors mounted on substrate All inputs, outputs and clocks fully TTL compatible 72 pin Single in-Line Memory Module (L-SIM-72-12) with 22

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