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HYM368025S - 8M x 36-Bit EDO - DRAM Module

General Description

EDO-DRAM Module (access time 50 ns) EDO-DRAM Module (access time 60 ns) EDO-DRAM Module (access time 50 ns) EDO-DRAM Module (access time 60 ns) Semiconductor Group 2 HYM 368025S/GS-50/-60 8M × 36-Bit EDO-Module Pin Configuration Pin Names VSS 1 DQ0 2 DQ18 3 DQ1 4 DQ19 5 DQ2 6 DQ20 7 DQ3 8 DQ21

Key Features

  • sh cycle, before proper device operation is achieved.

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Full PDF Text Transcription for HYM368025S (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for HYM368025S. For precise diagrams, and layout, please refer to the original PDF.

8M x 36-Bit EDO - DRAM Module HYM 368025S/GS-50/-60 • SIMM modules with 8 388 608 words by 36-bit organization in two banks for PC main memory applications Fast access an...

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ganization in two banks for PC main memory applications Fast access and cycle time 50 ns access time 84 ns cycle time (-50 version) 60 ns access time 104 ns cycle time (-60 version) Hyper Page Mode (EDO) capability 20 ns cycle time (-50 version) 25 ns cycle time (-60 version) Single + 5 V (± 10 %) supply Low power dissipation max. 6820 mW active (-50 version) max. 6160 mW active (-60 version) CMOS – 132 mW standby TTL –264 mW standby CAS-before-RAS refresh RAS-only-refresh Hidden-refresh Decoupling capacitors mounted on substrate All inputs, outputs and clocks fully TTL compatible 72 pin Single in-Line Memory Module (L-SIM

More Datasheets from Siemens Semiconductor Group (now Infineon)

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