HYM64V2005GU-60 Datasheet | Siemens Semiconductor Group

3.3V 2M × 64-Bit EDO-DRAM Module 3.3V 2M x 72-Bit EDO-DRAM Module 168pin unbuffered DIMM Module with serial presence detect HYM64V2005GU-50/-60 HYM72V2005GU-50/-60 - 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual In-Line Memory Module for PC main memory applications 1 bank 2M x 64, 2M x 72 organisation Optimized for byte-write non-parity or ECC applications Extended Data Out (EDO) Performance: -50 t RAC t CAC t AA t RC t HPC RAS Access Time CAS Access Time Access Time from Address Cycle Time EDO Mode Cycle Time 50 ns 13 ns 25 ns 84 ns 20 ns -60 60 ns 15 ns 30 ns 104 ns 25 ns - - - - - - - - - - - - - - Single +3.3 V ± 0.3 V Power Supply CAS-before-RAS refresh, RAS-only-refresh Decoupling capacitors mounted on substrate All inputs, outputs and clocks are fully LV-TTL patible Serial presence detects (optional) Utilizes 2M × 8 -DRAMs in SOJ packages 2048 refresh cycles / 32 ms with 11 / 10 addressing (Row / Column) Gold contact pad Card Size: 133,35mm x 25,40 mm x 5,30 mm This DRAM product module family is intended to be fully pin and architecture patible with the 168pin unbuffered SDRAM DIMM module family Semiconductor Group HYM 64(72)V2005GU-50/-60 2M x 64/72 DRAM Module The HYM64(72)V2005GU-50/-60 are industry standard 168-pin 8-byte Dual In-Line Memory Modules (DIMMs) which are organized as 2M x 64 and 2M x 72 high speed memory arrays designed with EDO DRAMs for non-parity and ECC applications. The DIMMs use eight 2M x 8 EDO DRAMs for the 2M x 64 organisation and nine 2M x 8 DRAMs for the 2M x 72 organisation, both in SOJ packages. Decoupling capacitors are mounted on the PC board. The DIMMs use optional serial presence detects implemented via a serial E 2PROM using the two pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes of serial PD data are available to the customer. All 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133,35 mm long spacesaving footprint. Ordering...