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HYM72V2005GS-50 - 2M x 72-Bit EDO-DRAM Module

General Description

Pin Names A0-A11,B0 A0-A10,B0 DQ0 - DQ71 RAS0, RAS2 CAS0 , CAS2 WE0, WE2 OE0, OE2 Vcc Vss PD1 - PD8 PDE ID0 , ID1 N.C.

Key Features

  • ite Cycle Read-write cycle time RAS to WE delay time CAS to.

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Full PDF Text Transcription for HYM72V2005GS-50 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for HYM72V2005GS-50. For precise diagrams, and layout, please refer to the original PDF.

2M × 72-Bit EDO-DRAM Module (ECC - Module) 168 pin buffered DIMM Module HYM 72V2005GS-50/-60 • 168 pin JEDEC Standard, Buffered 8 Byte Dual In-Line Memory Module for PC m...

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in JEDEC Standard, Buffered 8 Byte Dual In-Line Memory Module for PC main memory applications 1 bank 2 M x 72 organisation Optimized for ECC applications Extended Data Out (EDO) Performance: -50 tRAC tCAC tAA tRC tHPC RAS access time CAS access time Access time from address Read/Write cycle time Fast page mode cycle time 50 18 30 84 20 -60 60 20 35 104 25 ns ns ns ns ns • • • • • • • • • • • • • • • Single + 3.3V ± 0.

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