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HYS72V1000GU-50 - 3.3V 1M x 64-Bit SDRAM Module 3.3V 1M x 72-Bit SDRAM Module

Description

A0-A10 A11 (BS) DQ0 - DQ63 CB0-CB7 RAS CAS WE CKE CLK0 - CLK3 DQMB0 - DQMB7 CS0 - CS3 Vcc Vss SCL SDA N.C.

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3.3V 1M x 64-Bit SDRAM Module 3.3V 1M x 72-Bit SDRAM Module 168 pin unbuffered DIMM Modules HYS64V1000GS-10/-12/-15 HYS72V1000GS-10/-12/-15 Target Information • 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual-In-Line SDRAM Module 1 bank 1M x 64, 1M x 72 organisation Optimized for byte-write non-parity or ECC applications JEDEC standard Synchronous DRAMs (SDRAM) Performance: -10 fCK tCK3 tAC3 Clock frequency Clock cycle time Clock access time CAS latency = 3 • • • • -12 83 12 11 -15 66 15 13 Units MHz ns ns 100 10 9 • • • • • • • • • • • Single +3.3V(± 0.
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