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MGP3006X6 - GHz PLL with I2C Bus and Four Chip Addresses

General Description

Tuning Section UHF/VHF REF The tuner signal is capacitively coupled at the UHF/VHF-input and subsequently amplified.

The reference input REF should be decoupled to ground using a capacitor of low series inductance.

Key Features

  • q q q q q q 1-chip system for MPU-control (I2C Bus) 4 programmable chip addresses Short pull-in time for quick channel switch-over and optimized loop stability 3 high-current band switch outputs (20 mA) Software-compatible with SDA 3202 series Oxis III technology P-DSO-16-1 Type MGP 3006X6 MGP 3006X6 Ordering Code Q67000-H5113 Q67006-H5113 Package P-DSO-16-1 (SMD) P-DSO-16-1 Tape & Reel (SMD) Combined with a VCO (tuner), the MGP 3006X6 device, with four hard-switched chip addresses, forms.

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GHz PLL with I2C Bus and Four Chip Addresses MGP 3006X6 Bipolar IC Features q q q q q q 1-chip system for MPU-control (I2C Bus) 4 programmable chip addresses Short pull-in time for quick channel switch-over and optimized loop stability 3 high-current band switch outputs (20 mA) Software-compatible with SDA 3202 series Oxis III technology P-DSO-16-1 Type MGP 3006X6 MGP 3006X6 Ordering Code Q67000-H5113 Q67006-H5113 Package P-DSO-16-1 (SMD) P-DSO-16-1 Tape & Reel (SMD) Combined with a VCO (tuner), the MGP 3006X6 device, with four hard-switched chip addresses, forms a digitally programmable phase-locked loop for use in television sets with PLL-frequency synthesis tuning.